loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 37.out
1 GPR0 0000000000001AF3
2 GPR1 0000000000000000
3 GPR2 0000000000088911
4 GPR3 0000000000000000
5 GPR4 0000000001000014
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 FFFFFFFFFFFFFF8E
9 GPR8 0000000000088912
10 GPR9 0000000000000001
11 GPR10 E381FFFF800007FF
12 GPR11 0000000000000000
13 GPR12 0000000000000001
14 GPR13 0000000000000000
15 GPR14 FFFFFFFFFFFFFFFF
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFFFFFFFFF
18 GPR17 0000000050000000
19 GPR18 0000000000000000
20 GPR19 0000000000000E40
21 GPR20 FFFFFFFFFFFFFFFE
22 GPR21 0000000000088912
23 GPR22 FFFFFFFFFFFFFFFE
24 GPR23 0000000000088912
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 FF9FFFFFFFFFFFFF
30 GPR29 FFFFFFFFFFFFF1C0
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000051190253
34 LR 0000000000000000
35 CTR 000000000001C021
36 XER 0000000080000000
37