loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 373.out
1 GPR0 FFFFFFF7FFFFC152
2 GPR1 FFFFFFFFBB4E663F
3 GPR2 0000000000000000
4 GPR3 0000000000000020
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000008963338
8 GPR7 0000000000000000
9 GPR8 000000080000000E
10 GPR9 0000000000000002
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000901100
14 GPR13 0000000000000020
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 FFFFFFFF00000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFFFFD
23 GPR22 0000000000000000
24 GPR23 0000000000007C14
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 000000000001C020
29 GPR28 FFFFFC1400000000
30 GPR29 0000000000000020
31 GPR30 000000000001C020
32 GPR31
33 CR 0000000050F87000
34 LR FFFFFFFFFFFFF800
35 CTR FFFFFFFFFFFFFFFF
36 XER 00000000C0080000
37