loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 376.out
1 GPR0 000000000003805B
2 GPR1 0000000000002FE4
3 GPR2 000000000001C02E
4 GPR3 0000000000000000
5 GPR4 FFFFFFFFFFFE3FD2
6 GPR5 000000000000000C
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFFFE
10 GPR9 000000006A910000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 000000000001C02D
14 GPR13 FFFFFFFFFFFE3FD1
15 GPR14 0000000000000000
16 GPR15 000000000001C02D
17 GPR16 0000000000000000
18 GPR17 000000000001C020
19 GPR18 000000001D300003
20 GPR19 FFFFFFFFFFFFFFFD
21 GPR20 FFFFFFFFFFFFFFFF
22 GPR21 0000000000000000
23 GPR22 000000000001C02F
24 GPR23 000000001D300000
25 GPR24 FFFFFFFFFFFE3FDE
26 GPR25 0000000000000000
27 GPR26 0000001000000010
28 GPR27 0000000000000000
29 GPR28 FFFFFFFFFFFFFFF3
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 000000005FFE3F9F
34 LR 0000000000000000
35 CTR 00000000FFFFFFE5
36 XER 0000000080000000
37