loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 385.out
1 GPR0 0000000000000000
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 00000000E0007FFC
6 GPR5 0000000000000000
7 GPR6 000000000001817F
8 GPR7 0000000000000003
9 GPR8 0000000000000020
10 GPR9 0000000000000000
11 GPR10 0000000039904544
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFFFFB
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFFFD420
21 GPR20 0000000000000000
22 GPR21 0000000100000000
23 GPR22 00000000E0007FFC
24 GPR23 00004608C0000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 000000000001C038
31 GPR30 0000000028000000
32 GPR31
33 CR 0000000000004044
34 LR 000000001D370000
35 CTR FFFFFFFFFE2D2138
36 XER 00000000E00C0100
37