loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 396.out
1 GPR0 0000000000000000
2 GPR1 00000000394B0020
3 GPR2 0000004000000040
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000010000
11 GPR10 0000000000000000
12 GPR11 FFFFFFFFFFFFFFEE
13 GPR12 0000000000000000
14 GPR13 0200000000000000
15 GPR14 0000000000000000
16 GPR15 FFFFFFFFFFFFD9C6
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFD9C6
23 GPR22 0000000000000000
24 GPR23 0000000000000040
25 GPR24 FFFFFFFFFFFFD9C6
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFFFFF
28 GPR27 0000000000000000
29 GPR28 0000000000000004
30 GPR29 FFFFFFFFFFFFFFE8
31 GPR30 FFFFFFFFFFFFD9C6
32 GPR31
33 CR 00000000321735A9
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000000
37