loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 399.out
1 GPR0 0000000000000000
2 GPR1 0000003F80000000
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000003F7FFFFFF9
5 GPR4 0000000000000010
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 00000000FFFFFFF7
9 GPR8 0000000000000000
10 GPR9 FFFFFFFFFFFFFFFF
11 GPR10 0000000000000040
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFFFFFF
14 GPR13 000000000000001F
15 GPR14 FFFFFFFFFFFFFFFD
16 GPR15 0000002000000020
17 GPR16 00000000F7BDEF7C
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 00000000F7BDEF7C
20 GPR19 FFFFFFE000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000002
26 GPR25 0000000000000007
27 GPR26 000000000001C020
28 GPR27 0000000000000014
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 FFFFFFFFFFFFFFF9
32 GPR31
33 CR 000000005B9953FF
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 00000000C0080000
37