loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 413.out
1 GPR0 FFFFFFFFB0B4C491
2 GPR1 FFFFFFFFFFFFFFF9
3 GPR2 FFFEFFFFFFFE3FFA
4 GPR3 FFFFFFFFFFFFFFFF
5 GPR4 0001C0010001C001
6 GPR5 0000000000000000
7 GPR6 0000000000000041
8 GPR7 00000000817C03E0
9 GPR8 0000070808080808
10 GPR9 0000000000000000
11 GPR10 FFFEFFFFFFFFFFFF
12 GPR11 0000000000000000
13 GPR12 000000000019B6F0
14 GPR13 FFFEFFFFFFFC7FF5
15 GPR14 FFFFFFFFFFFFFFFF
16 GPR15 0000000000000000
17 GPR16 00000000817C26D8
18 GPR17 FFFFFFFFFFFE3FF9
19 GPR18 FFFF7FFFFFFE3FF9
20 GPR19 000000000019B6F0
21 GPR20 FFFEFFFFFFFE3FFA
22 GPR21 00007FFFFFFFFFFF
23 GPR22 0000000000000004
24 GPR23 FFFFFFFFFFFFFFFF
25 GPR24 80003FFFFFE00000
26 GPR25 FFFFFFFFFFFFFFF0
27 GPR26 00000000000022F8
28 GPR27 0000000000000040
29 GPR28 0000000030000000
30 GPR29 0000000000000000
31 GPR30 000000000001C005
32 GPR31
33 CR 0000000096DF0459
34 LR 0000000000000000
35 CTR FFFFFFFFFFFFFFFF
36 XER 00000000A0040040
37