loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 415.out
1 GPR0 FC00000000003BB9
2 GPR1 90000000000001C1
3 GPR2 0000000000000000
4 GPR3 0000A8C8ED305B50
5 GPR4 FFFFFFFFFFFFFFC6
6 GPR5 FFFFFFFFFFFF3DB3
7 GPR6 00000000000206E6
8 GPR7 000000000001C020
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 03FFFFFFFFFE6366
14 GPR13 FFFFFFFFFFFE7BB7
15 GPR14 0000000005000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 FFFFFFFFFFFF9196
20 GPR19 0000000000000020
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFFFFF9B4F
24 GPR23 0000000000000000
25 GPR24 0000000000018448
26 GPR25 0000000000006740
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 000000000001C002
30 GPR29 0000A8C8ED305B50
31 GPR30 FFFFFFFFFFFF9196
32 GPR31
33 CR 00000000851C45D9
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 000000000001C002
37