loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 437.out
1 GPR0 0000000000000000
2 GPR1 0000000000000001
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 FFFFFFFFFFFFFFBF
6 GPR5 0000000000000000
7 GPR6 0000000000000020
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 FFFFFFFFFFFFFFFF
12 GPR11 000000000000524D
13 GPR12 FFFFFFFFFFFFFFF0
14 GPR13 0000000000000000
15 GPR14 000000000000002F
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 000000000000276B
28 GPR27 000000000000524D
29 GPR28 000000000000524D
30 GPR29 FFFFFFFFFFFFFFFF
31 GPR30 FFFFFFFFFFFFFFFF
32 GPR31
33 CR 0000000092511105
34 LR FFFFFFFFFFFE7FE7
35 CTR 0000000000000000
36 XER 00000000A0040000
37