loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 449.out
1 GPR0 0E38E3AE38E38E18
2 GPR1 0000000000000000
3 GPR2 00000F8000000000
4 GPR3 0000000001881C00
5 GPR4 0000000000000040
6 GPR5 7FFFFFFFFFFFFF7F
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 0000000000000000
11 GPR10 FFFFFFFFFFFE3FDF
12 GPR11 0000000000000000
13 GPR12 000000000000001C
14 GPR13 0000000000000000
15 GPR14 FFFFFFFFFFFFFFFF
16 GPR15 00000F8000000000
17 GPR16 FFFFFFFFFFFFFFFF
18 GPR17 0000000000000020
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000001
23 GPR22 0001F00000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 7FFFFFFFFFFFFF7E
28 GPR27 0000000000000010
29 GPR28 0000000000000040
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000050E03419
34 LR 0000002000000020
35 CTR 000000000000FFFF
36 XER 00000000A0040000
37