loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 459.out
1 GPR0 3333333333333332
2 GPR1 11D5955211C00002
3 GPR2 FFFFFFFFFFFFFFFE
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 000000000016D9CA
7 GPR6 FFFFFFC1000007FD
8 GPR7 3333333333333332
9 GPR8 0000000000000000
10 GPR9 0808080808080705
11 GPR10 9990000099999999
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFFFFE4001
18 GPR17 00000000000073EF
19 GPR18 FFFFFFFF80000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFFFFF
23 GPR22 0000000000000000
24 GPR23 FFFFFFFFFFFEB6DC
25 GPR24 666FFFFF66666667
26 GPR25 0000000000000025
27 GPR26 0000000080000000
28 GPR27 FFFFFFFFFF000000
29 GPR28 FFFFFFFFFFFFFFFF
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000033500158
34 LR FFFFFFFFFFFFFFFD
35 CTR 0000000000112358
36 XER 00000000C0080001
37