loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 463.out
1 GPR0 000000000000000C
2 GPR1 000000000001C020
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 C020000000000000
8 GPR7 FFFFFFFFFFFFFFFF
9 GPR8 0000004000000001
10 GPR9 0000000000000000
11 GPR10 FFFFFFFF0805FFF4
12 GPR11 0160000000000000
13 GPR12 00000000F7FA000B
14 GPR13 0000004000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 00000000F7FA000C
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 00000000F7FBC02B
22 GPR21 0000000000000000
23 GPR22 0000000000000040
24 GPR23 FFFFFFFFFFFE3FE0
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 000000000001C020
29 GPR28 0000000000000080
30 GPR29 0000000000000000
31 GPR30 00020019228000AA
32 GPR31
33 CR 000000005F054583
34 LR 0000000000000000
35 CTR 0000004000000000
36 XER 000000008000000C
37