loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 479.out
1 GPR0 FFFFFFFFFFFFB082
2 GPR1 FFFFFFFFFF0002C0
3 GPR2 0000000000000000
4 GPR3 000000000001F000
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 003F8000003E0000
14 GPR13 0000000000000000
15 GPR14 FFFFFFFFFFFFFFFE
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFFFFFFFFF
24 GPR23 000000000001C014
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000030339415
34 LR 0000000090000000
35 CTR 0000000000000000
36 XER 00000000E00C0000
37