loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 480.out
1 GPR0 0000000000000000
2 GPR1 0000000000000001
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 000000000001C018
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 FFFFFFFFFFFFFFFF
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000020
13 GPR12 0000000000000000
14 GPR13 FFFFFFFFFFFFFFFF
15 GPR14 FF00000007E0F3FF
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 FFFFFFFFFFFFFFFF
20 GPR19 0000000000000000
21 GPR20 FFFFFFFFFFFFFFFF
22 GPR21 000000000000399C
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 000000000000399C
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFF8BB3
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000030F843F0
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000100
37