loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 481.out
1 GPR0 00000080000000A0
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 000000000001C020
6 GPR5 0000000000900000
7 GPR6 FFFFFFFFFFFFC008
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000020
11 GPR10 0000000000000000
12 GPR11 DFFFF90107FFF900
13 GPR12 1FFFFFFFFFFFFFFF
14 GPR13 0000000000000000
15 GPR14 000000000000C008
16 GPR15 FFFFFFFFFFFFFFFF
17 GPR16 0000000000000000
18 GPR17 DFFFF90107FFF8FF
19 GPR18 0000000000000020
20 GPR19 000000000000C008
21 GPR20 FFFFFFFFFFFFFFFF
22 GPR21 0000000000000000
23 GPR22 DFFFF90107FFF900
24 GPR23 0000000000000000
25 GPR24 0000000000000002
26 GPR25 000000000001C020
27 GPR26 0000000000000000
28 GPR27 180000000000FFFF
29 GPR28 FFFFFFFFFFFFFFFD
30 GPR29 FFFFFFFFFFFFFFFF
31 GPR30 0000000000000004
32 GPR31
33 CR 0000000051905700
34 LR FFFFFFFFFFFFFFFF
35 CTR FFFFFFFFFFFFFFFC
36 XER 00000000A0046FF2
37