loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 483.out
1 GPR0 080808027E31653D
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 FFFFFFCFF6BFA70A
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFF1FF48
7 GPR6 0000000000000000
8 GPR7 0000000000007428
9 GPR8 0000000000000000
10 GPR9 0000000033C10995
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000003009400007
14 GPR13 000000000001C01F
15 GPR14 0000000067FC6733
16 GPR15 0000000000001B37
17 GPR16 FFFFFFFFFFFFA70F
18 GPR17 03FFFFFFFFFFF8FF
19 GPR18 000000000000001C
20 GPR19 0000000000000008
21 GPR20 0000000000001B36
22 GPR21 FFFFFFFFFFFFFFFF
23 GPR22 0000000067FCC025
24 GPR23 FFFFFFFFFFFE3FE0
25 GPR24 0000000000000000
26 GPR25 00000000000058F2
27 GPR26 00000000000058F1
28 GPR27 E82E1FF200000000
29 GPR28 FFFFFFFFFFED7F4E
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000033C10995
34 LR FFFFFFFFFFFE3FE0
35 CTR 0000000000000003
36 XER 00000000A0040001
37