loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 493.out
1 GPR0 FFFFFFFFFFFF7A98
2 GPR1 0000000000000003
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000000051000290
5 GPR4 FFFFFFFFFFFFFFD9
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFF765D
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000180
11 GPR10 FFFFFFFFFFFE3FD7
12 GPR11 0000000000008381
13 GPR12 0000000000000000
14 GPR13 0000000006EB3E45
15 GPR14 0000000000000240
16 GPR15 FFFFFFFFFFFFFFE8
17 GPR16 0000000051000290
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 FFFFFFFFFFFFFFFE
20 GPR19 FFFFFFFFFFFE3FD7
21 GPR20 00000000000000C0
22 GPR21 000001FF00000003
23 GPR22 0000000000000001
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 000000001FFFFFF0
27 GPR26 0000000000000025
28 GPR27 FFFFFE0100008564
29 GPR28 000001FF00000003
30 GPR29 0000000000008542
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000055001990
34 LR FFFFFFFFFFFFFFFB
35 CTR 0000000000000000
36 XER 00000000A0040000
37