loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 494.out
1 GPR0 0000000023AC0000
2 GPR1 FFFFFFFF00000011
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000003070011
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 00000000FFFFFF00
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 00000000FFFFFFEE
13 GPR12 0000000000000000
14 GPR13 0000000003070008
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000040
20 GPR19 00000000FFFFFFEF
21 GPR20 00000000FFFFFFEE
22 GPR21 000000000001C020
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000008
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000040
30 GPR29 0000000000000000
31 GPR30 FFFFFFFF00000012
32 GPR31
33 CR 0000000050579045
34 LR 0000000000000000
35 CTR 0000000000000002
36 XER 00000000A0040000
37