loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 505.out
1 GPR0 00FFC00100FFFFA0
2 GPR1 00FFFFFF00FFFFFE
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 8001D0028001BED3
16 GPR15 0000000000000001
17 GPR16 0000000000000000
18 GPR17 00FFFFFF00FFFFFF
19 GPR18 0000000000000000
20 GPR19 1C0200003FFE0000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 FFFFFFFFFFFE3FDF
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFFFFF
28 GPR27 7FFE2FFD7FFDD711
29 GPR28 000000000001C020
30 GPR29 0000000000003FFF
31 GPR30 3FFDFFFF3FFDFFFF
32 GPR31
33 CR 0000000095229929
34 LR 0000000000000000
35 CTR 000000000001C022
36 XER 00000000A005C020
37