loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 508.out
1 GPR0 FFFFFFFFFFFE3FE0
2 GPR1 0000172000000000
3 GPR2 0000000000000006
4 GPR3 0000000200000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000003
8 GPR7 0000000000000006
9 GPR8 0000000000000000
10 GPR9 FFFFFFFFFFFFFFFE
11 GPR10 0000000000000000
12 GPR11 FFFFFFFFFC000000
13 GPR12 000000000001C020
14 GPR13 FFFFFFFF5F12BF00
15 GPR14 0000000000000000
16 GPR15 0000000000000002
17 GPR16 0000000000005C80
18 GPR17 FFFFFFFFA0ED50FF
19 GPR18 0000000000000000
20 GPR19 000000005F12AF00
21 GPR20 0000000000000000
22 GPR21 000000000D51AF00
23 GPR22 0000000000000000
24 GPR23 FFFFFFFDFFFFFFFF
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFFFFF
28 GPR27 FFFFFFFFFC000000
29 GPR28 0000000000000020
30 GPR29 00000000FFFFF000
31 GPR30 0000000000000040
32 GPR31
33 CR 0000000020105029
34 LR 000000005F12AF00
35 CTR FFFFFFFFFFFFFFFF
36 XER 0000000020040000
37