loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 511.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 FFFFFFFFFFFFFFFF
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 00000000255E0000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000020
15 GPR14 FFFFFFFFFFFFFFFF
16 GPR15 000000000001C020
17 GPR16 FFFFFFFF12492492
18 GPR17 0000000000000100
19 GPR18 0000000000000000
20 GPR19 0000000000000040
21 GPR20 FFFFFFFFFFFFFF00
22 GPR21 0000000000000000
23 GPR22 0000000000000040
24 GPR23 0000000000000000
25 GPR24 000000000000000E
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000060
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000030952096
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 00000000A0040000
37