loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 532.out
1 GPR0 FFFFFFFFFFFE235F
2 GPR1 0000000000000015
3 GPR2 0000000000000000
4 GPR3 FFFFFFFFFFFFFE04
5 GPR4 0000000000000040
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 4000060240000602
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000003012
14 GPR13 0000000000000015
15 GPR14 000000000001C020
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000020
21 GPR20 FFFFFFFFFFFFFFFF
22 GPR21 0000000000000211
23 GPR22 0000000000000004
24 GPR23 0000000000000000
25 GPR24 FFFFFFFFFFFFFDEC
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000050490E53
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000000
37