loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 534.out
1 GPR0 0000000000000000
2 GPR1 0000000000000040
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 FFFFFFFF99000029
7 GPR6 000000000001C020
8 GPR7 0000000000248FAC
9 GPR8 0000002000000020
10 GPR9 0000000000000000
11 GPR10 000000000001C020
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFE3FDF
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000005F30
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000098FE4008
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 FFFFFFFFFFFFFFFF
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000099000029
28 GPR27 0000000000000000
29 GPR28 000000000000002F
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000039000029
34 LR 0000000000000000
35 CTR FFFFFFFFFFFFF0FE
36 XER 00000000E00C0000
37