loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 535.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000000000000
3 GPR2 0000000005E00000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 FFFFFFFFFFFFFFFF
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFFFD0000023D
14 GPR13 0000000000000000
15 GPR14 FFFFFFFFFFFFFFFE
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 000000008000692E
19 GPR18 0000000000001DF5
20 GPR19 FFFFFFFD0000023D
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 000000000001C020
26 GPR25 0000000000000000
27 GPR26 0000000000023A7F
28 GPR27 0000000000000001
29 GPR28 0000000000000000
30 GPR29 0000000000000020
31 GPR30 0000000027800000
32 GPR31
33 CR 0000000039881025
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 000000008000692E
37