loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 536.out
1 GPR0 0000000000000000
2 GPR1 0000000090000000
3 GPR2 0000000000000000
4 GPR3 0000001400000014
5 GPR4 000000000000000A
6 GPR5 0000000000000002
7 GPR6 FFFFFFFFFFFFF800
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000014
11 GPR10 0000000000000000
12 GPR11 0000000002000000
13 GPR12 0000000000003B2F
14 GPR13 FFFFFFFFFFFFFFFE
15 GPR14 0000000050000000
16 GPR15 0000000000000000
17 GPR16 0000000000000014
18 GPR17 0000000000000014
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000006
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 000000000000004F
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000006
30 GPR29 0000000000000000
31 GPR30 FFFFFFFF3D39C7AF
32 GPR31
33 CR 000000005009C0D4
34 LR FFFFFFFF8E379F00
35 CTR 0000000044B00000
36 XER 0000000080000000
37