loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 55.out
1 GPR0 0000000000001BC7
2 GPR1 0000000000000000
3 GPR2 000000000001C020
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000020
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 FFFFFFFFAC57C7F8
11 GPR10 0000000000000000
12 GPR11 0000000000001BE7
13 GPR12 00FF0000FFFFE418
14 GPR13 0000000090000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFFFFFFF
21 GPR20 0000000000000028
22 GPR21 FFFFFFFFFFFFFFFE
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 00000000000053A2
28 GPR27 00000000553010F2
29 GPR28 0000000000000000
30 GPR29 00000000119A0001
31 GPR30 000000000000003F
32 GPR31
33 CR 0000000099301952
34 LR 000000000000891B
35 CTR 0000000000000000
36 XER 00000000A0040000
37