loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 567.out
1 GPR0 0000000000000000
2 GPR1 000000000000000F
3 GPR2 0000000056E5FFFF
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 1397340000000016
7 GPR6 00000000FFFFF7FC
8 GPR7 0000000100000803
9 GPR8 0000000000000000
10 GPR9 0000000100000803
11 GPR10 000000000001C020
12 GPR11 000000000001C000
13 GPR12 00000000FFC00000
14 GPR13 0000133347698000
15 GPR14 FFEEDCA718A2CFCC
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 EE01A66823110000
21 GPR20 FFFFFFFFFFFFDA54
22 GPR21 FFFFFFFFFFFFFFFF
23 GPR22 0000000000000000
24 GPR23 0000133347698000
25 GPR24 0000000000000000
26 GPR25 0000133347698000
27 GPR26 00000000000027DA
28 GPR27 00000000FFFFF7FC
29 GPR28 000000000001C000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000059555595
34 LR 00000000FFFFF7FC
35 CTR FFFFFFFF000007FF
36 XER 0000000080000000
37