loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 610.out
1 GPR0 0000000000000000
2 GPR1 0000000000E01000
3 GPR2 0000000000000000
4 GPR3 000000000001C02B
5 GPR4 00000000A94E6DE1
6 GPR5 0000000000000001
7 GPR6 00000000FD770000
8 GPR7 000000000000E9B0
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 000000006C170000
14 GPR13 0000000000000000
15 GPR14 000000003D376DE1
16 GPR15 0000000000000001
17 GPR16 FFFFFFFFFFFFFFFF
18 GPR17 0000000000000001
19 GPR18 FFFFFFFFA6BE28A6
20 GPR19 000000000001C02B
21 GPR20 0000000000000000
22 GPR21 00000000FFFFFFFE
23 GPR22 0000000000000000
24 GPR23 000000000000E9B0
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 000000000000E9B0
28 GPR27 000000000000487C
29 GPR28 00000000FD76FFFF
30 GPR29 000000003D370000
31 GPR30 FFFFFFFFFFFFFFFE
32 GPR31
33 CR 0000000050050020
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080080000
37