loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 619.out
1 GPR0 0000000000000000
2 GPR1 FFFFFFFFFFFE3FE1
3 GPR2 0000000000000001
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000020
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 000000000001C01F
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFBF49FFFF
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 000000000001C01F
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFF9EF4
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000040
27 GPR26 0000000000006BC7
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000090904FFE
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000000
37