loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 621.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000000000040
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 000000000000C9AB
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 FFFFFFFFFFFFFFFF
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFC001F6BA
21 GPR20 0000000045710000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFFFFFFFF
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000097FE0945
34 LR 000000FFFFFFFFFE
35 CTR 0000000000000027
36 XER 0000000080010000
37