loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 626.out
1 GPR0 FFFFFFFFFF8AB8F7
2 GPR1 FFFFFFFFFF8AB8F7
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000000000000000
5 GPR4 FFFFFFFFFFFF8E85
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000003
9 GPR8 0000000000000000
10 GPR9 0000002000000020
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFF8AB8F6
14 GPR13 FFFFFFFFFFFFFFFF
15 GPR14 FFFFFFFF8D170480
16 GPR15 0000000000003A7E
17 GPR16 0000000000002800
18 GPR17 FFFFFFFFFF89E690
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFF003C01F
24 GPR23 0000000000000000
25 GPR24 000000000FFE0000
26 GPR25 0000000050000000
27 GPR26 FFFFFFFFFFFFFF00
28 GPR27 00000000000000FF
29 GPR28 0000000000000000
30 GPR29 00000000000000FF
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000030409300
34 LR 0000000000000000
35 CTR 00000000000000FF
36 XER 00000000C0080000
37