loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 628.out
1 GPR0 000000000001C038
2 GPR1 0000000000000000
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000000000000000
5 GPR4 FFFFFFFFFFFFFFFF
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFFBE20
8 GPR7 0000000000000000
9 GPR8 0000000000000004
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000020
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFFFFFFF07
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 FFFFFFFFFFFFFFBF
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 00000000FFFFFB0A
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFFFFFFFF
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFFFFFF
31 GPR30 000000000001C020
32 GPR31
33 CR 0000000020FCA35D
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000000000000
37