loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 63.out
1 GPR0 FFFFFFFF3FFBF252
2 GPR1 0000000000000000
3 GPR2 0000038040000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 000000000001C020
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000040
12 GPR11 0000E0240000E024
13 GPR12 0000000000000000
14 GPR13 FFFFFFFF90F5F287
15 GPR14 000000000000001C
16 GPR15 00001C0200000000
17 GPR16 FFFFFFFFF000235B
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 000000000000003F
21 GPR20 0000000000000000
22 GPR21 0000000000000001
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 FFFFFFFF3FFBF253
27 GPR26 0000000000050FA0
28 GPR27 0000000050FA0034
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 FFFFE3FDFFFFFFC0
32 GPR31
33 CR 000000003AB3003F
34 LR FFFFFFFFC23FFFFE
35 CTR 0000000000000000
36 XER 0000000080080040
37