loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 646.out
1 GPR0 000002C370A26BFF
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 0000000000FF0000
5 GPR4 FFFFFFFFFFFFFFFA
6 GPR5 0000000000000000
7 GPR6 0000000000004000
8 GPR7 7FFFFFFFE1F3DA00
9 GPR8 FFFFFFC3E783FF00
10 GPR9 00000000C0000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 000000000001C020
14 GPR13 FFFFFFECFC4FF400
15 GPR14 00000061C0000001
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFD0000000
18 GPR17 0000000000005C9A
19 GPR18 0000000000000020
20 GPR19 800000001F0B2600
21 GPR20 FFFFFFFFFFFFFFFF
22 GPR21 7FFFFFFFE1F3C1FF
23 GPR22 FFFFFD3CA0A22800
24 GPR23 000000006D950000
25 GPR24 FFFFFFFFFFFF662D
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000005C9A
29 GPR28 FFFFFFFFFFFFFFFE
30 GPR29 FE1F3C1FF80003FF
31 GPR30 FFFFFFF800000000
32 GPR31
33 CR 000000005F578901
34 LR 0000000000000001
35 CTR 0000000000000000
36 XER 00000000E0080000
37