loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 679.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 000000000001C03C
3 GPR2 0000000000000000
4 GPR3 000000000000130E
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFFFFFF
8 GPR7 0000000000000000
9 GPR8 000000000001FE00
10 GPR9 000000008003FFFF
11 GPR10 0000000000000010
12 GPR11 000000000001FE00
13 GPR12 0000000000000000
14 GPR13 0D1C0000811FFFFF
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0D1C0000011C0000
18 GPR17 0000000000000000
19 GPR18 000000000001C03C
20 GPR19 F9FFFFFFFFFFFFF1
21 GPR20 03FFFFFFFFFBD48A
22 GPR21 FFFFFFFFFFFFFFEF
23 GPR22 FFFFFFFFFFFFFFFF
24 GPR23 FFFFFFFFFFFFFFFF
25 GPR24 FFFFFC92BEA1E5BF
26 GPR25 0000000000000000
27 GPR26 0000000000800000
28 GPR27 0000000000003470
29 GPR28 0000000000000000
30 GPR29 0003FFFFFFFFFFFF
31 GPR30 0000000000003470
32 GPR31
33 CR 000000009010E412
34 LR 0000000000000000
35 CTR FFFFFFFFFFFFFFFC
36 XER 000000008003FFFF
37