loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 690.out
1 GPR0 FFFFFFFFFFFE3F9E
2 GPR1 0000000000000001
3 GPR2 0000000000000000
4 GPR3 0000000000003DCD
5 GPR4 0000000000000001
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 000000000FFFFFFC
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 FFFFFFFFFFFFF0E7
12 GPR11 0001C021FFFFEC3B
13 GPR12 0000000000099A4D
14 GPR13 0000000000000000
15 GPR14 0000000000000020
16 GPR15 0000000000099A4D
17 GPR16 0000000000000001
18 GPR17 000000000001C020
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 000000000009C061
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000050005200
34 LR 000000000001C020
35 CTR 0000000000000000
36 XER 00000000C0080004
37