loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 727.out
1 GPR0 FFFFFFFFFFFFFFC5
2 GPR1 0000000000000000
3 GPR2 0000000000000040
4 GPR3 0000000000000020
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFFFFFFE
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 000000000000003A
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 FFFFFFFFFFFFFFFF
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFFFFFFF
21 GPR20 000000000000003A
22 GPR21 FFFFFFFFFFFFF8A0
23 GPR22 0000000000000000
24 GPR23 0000000000000020
25 GPR24 0000000000000000
26 GPR25 FFFE00000FFFFFFF
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000040
30 GPR29 0000000000000040
31 GPR30 FFFFFFFFFFFFFFBF
32 GPR31
33 CR 0000000053559C73
34 LR FFFFFFFFFFFFFFFF
35 CTR FFFFFFFFFFFFFFFF
36 XER 00000000A0040000
37