loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 737.out
1 GPR0 FFFFFFFFFFFFFD5D
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 000000000D7B6DE3
5 GPR4 FFFFFFFFFFFFFD5D
6 GPR5 0000000000000000
7 GPR6 000000000001C020
8 GPR7 FFFFFF800000CFFF
9 GPR8 FFFFF0001FFFFFFF
10 GPR9 FFFFFF80000007FE
11 GPR10 FFDFFFFFFFFFFFFF
12 GPR11 FFFFFFFFFFFFFFF9
13 GPR12 0000000000000000
14 GPR13 FFFFFFFFFFFFFFFE
15 GPR14 FFFFFF800000CFFF
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000005
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000015
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 FFFFFF80000007FE
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000007FFFFFF802
29 GPR28 FFFFFFFFFFFFFFFE
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000090548A54
34 LR 000000000000E87B
35 CTR 0000000000000000
36 XER 00000000A007FFFF
37