loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 740.out
1 GPR0 FFFFFFFFFFFFFFF2
2 GPR1 000000000000FFFF
3 GPR2 000000000000FFFF
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000090010080
9 GPR8 0000000000004735
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 FFFFFFFFFFFFFFFF
13 GPR12 FFFFFFFFCBC60000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 000000000000000C
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000004735
23 GPR22 0000000000005AE4
24 GPR23 0000000000000001
25 GPR24 000000003439FFFE
26 GPR25 0000000000000001
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFEF0177F
29 GPR28 00000000FFFFFFF2
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000034015080
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 00000000E0060000
37