loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 744.out
1 GPR0 FFFFE5DE25F21FA2
2 GPR1 FFFFFFFFBBDE41C5
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 000000007F800000
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 00001A20C8C65E68
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFBE3A
10 GPR9 FFFFFFFF9A4E41C3
11 GPR10 0000000065B1BE3C
12 GPR11 FFFFFFFFFFFFFFFF
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 000000C0000000BF
16 GPR15 00000000000009EA
17 GPR16 00000000000059D8
18 GPR17 0000CB6360000000
19 GPR18 FFFFFFFFFFFFFFFE
20 GPR19 00000000CEAA0000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFF9A4E41C5
23 GPR22 00000000000041C5
24 GPR23 0000000065B1CCC9
25 GPR24 FFFFFFFF9A4E41C4
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFFFFE
28 GPR27 FFFFFFFF9A4E41C5
29 GPR28 0000000000000000
30 GPR29 0000000065B1CCC9
31 GPR30 E3C0000000065B1B
32 GPR31
33 CR 000000000000419A
34 LR 00000004645D1C00
35 CTR 0000000000000E8E
36 XER 00000000A0000000
37