loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 749.out
1 GPR0 FFFFFFFFCBE4EF5B
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 0001D124CBE4EB1C
5 GPR4 0000000000000000
6 GPR5 C817FFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 FFFFFFFFFFFFFFFF
9 GPR8 0001D124CBE4EB1B
10 GPR9 FFFFFFFFFFFFEB1B
11 GPR10 0000000000000001
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 FFFFFFFFFFFFFFFF
15 GPR14 FFFFFFFFFFFFFFFF
16 GPR15 0000000000000000
17 GPR16 0000000025F27580
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 EEB10EAB497C76DC
21 GPR20 FFFFFFFFFFFFFFFF
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000055099590
25 GPR24 FFFFFFFFFFFFFFFF
26 GPR25 0001D124CBE4EAAB
27 GPR26 0000000000000000
28 GPR27 0000000000000001
29 GPR28 0001D124CBE4EB1C
30 GPR29 0000000000000020
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000095099590
34 LR 0000000000000000
35 CTR FFFFFFFFFFFFFFC3
36 XER 00000000C00A3FDF
37