loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 759.out
1 GPR0 FFFFFFFFFFFFDB64
2 GPR1 0000000000000000
3 GPR2 000000000001C00C
4 GPR3 0000000000000AC6
5 GPR4 00000012DA69CF4C
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0017C31C082B11A0
11 GPR10 588D08139869CF4C
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000020
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0017C31C082B11A1
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFDB64
23 GPR22 588D0800BE000000
24 GPR23 0000000000000000
25 GPR24 0000000000000001
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 000000000001C020
28 GPR27 000000000001C00C
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000006CA1
32 GPR31
33 CR 0000000050089139
34 LR 0000000000000000
35 CTR 000000000000E3FF
36 XER 00000000A0040001
37