loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 766.out
1 GPR0 0000000000000000
2 GPR1 0000000000016B76
3 GPR2 0000000000000005
4 GPR3 0000000000000001
5 GPR4 0000000000000005
6 GPR5 0000000000000006
7 GPR6 0000000000000038
8 GPR7 0000000000000040
9 GPR8 0000000000000000
10 GPR9 FFFFFFFFFFFFFFFF
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 000000000001C020
14 GPR13 00000000FFFFFFFE
15 GPR14 000000000001C020
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 000000000001C020
20 GPR19 FFFFFFFFFFFFFFFE
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFFFFFFFFA
24 GPR23 0000000000000020
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000004
29 GPR28 000000003F050C38
30 GPR29 0000000000000040
31 GPR30 0000000000000000
32 GPR31
33 CR 000000003F050038
34 LR 000000000001C03E
35 CTR FFFFFFFFFFFFFFFF
36 XER 0000000080004001
37