loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 777.out
1 GPR0 FFFFFFFF00000DFF
2 GPR1 0000000057D40000
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000008080806
7 GPR6 0700100007001000
8 GPR7 FFFFE000FFFFFFE1
9 GPR8 000000000001C020
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 000000000002A635
13 GPR12 0000000000000000
14 GPR13 00000000000239EA
15 GPR14 0000000000000400
16 GPR15 000000000001C004
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFFD59CA
21 GPR20 0000000000000000
22 GPR21 0000000000000020
23 GPR22 0000000000000000
24 GPR23 000000000001C020
25 GPR24 00000000FFFFFFDE
26 GPR25 0000000000000000
27 GPR26 000000000002A636
28 GPR27 00000000FFFFFFDE
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 000000000001C020
32 GPR31
33 CR 000000005A091005
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 000000008003FFFE
37