loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 782.out
1 GPR0 0000000000000000
2 GPR1 000000000001C020
3 GPR2 000000000001C020
4 GPR3 0000000000000000
5 GPR4 00000000000057D5
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFFFFFF
8 GPR7 FFFFFFFFFFFE3FDF
9 GPR8 000000000000607C
10 GPR9 FFFFFFFFFFFFFFF8
11 GPR10 0000000000000000
12 GPR11 FFFFFFFFFFFFA829
13 GPR12 0000000000000000
14 GPR13 0000000000000010
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFFFFFFFFF
18 GPR17 FFFFFFFFFFFF9F7C
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000005736
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000036410000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000005735
28 GPR27 0000000000000000
29 GPR28 FFFFFFFFFFFFFFFF
30 GPR29 0000000000005736
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000030009693
34 LR 00000000000057D5
35 CTR FFFFFFFFFFFFFFFF
36 XER 00000000A007E3FE
37