loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 788.out
1 GPR0 FFFFFFFFFFFFFFFE
2 GPR1 0000000000000020
3 GPR2 0000000014EC0000
4 GPR3 0000000000000000
5 GPR4 000000005621481D
6 GPR5 0000000000000020
7 GPR6 000000000001C013
8 GPR7 0000000000000000
9 GPR8 00007FFFC0000000
10 GPR9 0000000000000021
11 GPR10 0000000000000000
12 GPR11 FFFFFFFF7FFFFFFF
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 000000000001789E
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 0000000000000001
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFFFFF
23 GPR22 FFFFFFFFFFFFC538
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 FFFFFFFFFFFFFFFE
27 GPR26 FFFFFFFFA9DEFFFF
28 GPR27 0000000000000000
29 GPR28 0000000000000020
30 GPR29 0000000000000000
31 GPR30 000000000001789E
32 GPR31
33 CR 000000003899F993
34 LR 0000000000000000
35 CTR 0000000000000001
36 XER 0000000080000000
37