loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 792.out
1 GPR0 0000000000000000
2 GPR1 0000000000000000
3 GPR2 000000000001C020
4 GPR3 0000000000000000
5 GPR4 00000000000137B0
6 GPR5 0000000000000040
7 GPR6 0000000003F392CA
8 GPR7 0000000000000000
9 GPR8 00000000C0080000
10 GPR9 0000000000000000
11 GPR10 FFFFFFFFFFFE3FE0
12 GPR11 000000000012DA14
13 GPR12 0000000000000000
14 GPR13 FFFFFFFFBA1C0000
15 GPR14 00000000C0080000
16 GPR15 0000000000000020
17 GPR16 000000000012DA14
18 GPR17 FFFFFFFFBA1C0000
19 GPR18 FFFFFFFFFFFFFFFF
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFC41F
23 GPR22 0000000000000000
24 GPR23 00000000108893F6
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000003F409FD
29 GPR28 0000000000310000
30 GPR29 FFFFFFFFFFFE03FF
31 GPR30 0000000003340000
32 GPR31
33 CR 0000000099100015
34 LR FFFFFFFFFFFE3FE0
35 CTR 0000000000005BA8
36 XER 00000000A0040000
37