loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 802.out
1 GPR0 000000000001C020
2 GPR1 FFFFFFFFFFFFC01F
3 GPR2 000000008A940000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFFFF080
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000002
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFFFFD6
14 GPR13 FFFFFFFF756BFFFF
15 GPR14 0000000000000000
16 GPR15 FFFFFFFFFFFFB807
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFB807
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFF790D2
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFF773263C
23 GPR22 FFFFFFFFFFF790D2
24 GPR23 000000000001C028
25 GPR24 0000000000000000
26 GPR25 0000000000005000
27 GPR26 0000000000000F80
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 00000000005900C0
34 LR 0000000000005000
35 CTR 0000000000000000
36 XER 0000000080000000
37