loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 803.out
1 GPR0 0000000000000000
2 GPR1 FFFFFFFFFFFFFFFE
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 FFFFFFFFFFFFFFFE
9 GPR8 0000000000000001
10 GPR9 0000000000000005
11 GPR10 03FFFEFC5914E9BB
12 GPR11 0000000000000000
13 GPR12 0000000120E91D2A
14 GPR13 0000000000001663
15 GPR14 0000000000000006
16 GPR15 FFFFFFFFFFFFFFFF
17 GPR16 0000000000000000
18 GPR17 0000000000000001
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000001
25 GPR24 0000000000000000
26 GPR25 0808080808080808
27 GPR26 0000000000000000
28 GPR27 FFFFFF000000E9BB
29 GPR28 FFFFFFFFFFFFFFFF
30 GPR29 0808080808080808
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000051048E75
34 LR FFFFFFFFFFFFFFFD
35 CTR 0000000000000000
36 XER 000000008001C26D
37