loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 81.out
1 GPR0 0000000000000001
2 GPR1 FFFFFFFFFFFFFF1F
3 GPR2 0000000000000022
4 GPR3 00000000046F1CA2
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000002
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 00000000FFFF0004
14 GPR13 0000000000000004
15 GPR14 FFFFFFFFFFFFFFFF
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFFFFFFFFE
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFFFFFFF1F
24 GPR23 0000000000000000
25 GPR24 000007C3000007C2
26 GPR25 0000000000000040
27 GPR26 000000000001C020
28 GPR27 000000000001C034
29 GPR28 0000000000000000
30 GPR29 000007C2FFFFC092
31 GPR30 000000000001C034
32 GPR31
33 CR 00000000304D5910
34 LR 000000008003D507
35 CTR FFFFFFFFFFFFFFFF
36 XER 00000000C009C020
37